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SN74AHC138N-P2
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SN74AHC138N-P2

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  • 贸泽

起订量: 1696

  • 库存: 0
  • 单价: ¥1.28055
  • 数量:
    - +
  • 总计: ¥2,171.80
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规格参数

  • 制造厂商 德州仪器 (Texas)
  • 输出高电流, 输出低电流 -
  • 种类 -
  • 集成电路 -
  • 独立电路板 -
  • 电压供应源 -
  • 电源电压 -
  • 工作温度 -
  • 安装类别 -
  • 包装/外壳 -
  • 供应商设备包装 -
  • 部件状态 过时的

SN74AHC138N-P2 产品详情

The ’AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

Feature

  • Operating Range 2-V to 5.5-V VCC
  • Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
Description

The ’AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

SN74AHC138N-P2所属分类:信号开关/多路复用器/解码器,SN74AHC138N-P2 由 德州仪器 (Texas) 设计生产,可通过久芯网进行购买。SN74AHC138N-P2价格参考¥1.280545,你可以下载 SN74AHC138N-P2中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询SN74AHC138N-P2规格参数、现货库存、封装信息等信息!

德州仪器 (Texas)

德州仪器 (Texas)

德州仪器公司(TI)是一家开发模拟IC和嵌入式处理器的全球半导体设计和制造公司。通过雇用世界上最聪明的人,TI创造了塑造技术未来的创新。如今,TI正在帮助超过10万名客户改变未来。

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