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CDCL1810RGZT

  • 描述:种类: 扇出缓冲器(分配),分配器 输入比率 / 输出比率: 1:10 最大频率: 650 MHz 供应商设备包装: 48-VQFN(7x7) 工作温度: -40摄氏度~85摄氏度 安装类别: 表面安装
  • 品牌: 德州仪器 (Texas)
  • 交期:5-7 工作日
渠道:
  • 自营
  • 得捷
  • 贸泽

起订量: 40

  • 库存: 22995
  • 单价: ¥55.11847
  • 数量:
    - +
  • 总计: ¥2,204.74
在线询价

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规格参数

  • 部件状态 可供货
  • 电线数量 one
  • 工作温度 -40摄氏度~85摄氏度
  • 安装类别 表面安装
  • 输入差分 / 输出差分 Yes/Yes
  • 制造厂商 德州仪器 (Texas)
  • 输入比率 / 输出比率 1:10
  • 种类 扇出缓冲器(分配),分配器
  • 最大频率 650 MHz
  • 输入值 LVDS
  • 输出 CML
  • 电源电压 1.7伏~1.9伏
  • 包装/外壳 48-VFQFN外露衬垫
  • 供应商设备包装 48-VQFN(7x7)

CDCL1810RGZT 产品详情

The CDCL1810RGZT is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT = FIN/P, where: P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80.

The CDCL1810RGZT supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled.

With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810RGZT can support a single-ended clock input as outlined in Pin Configuration and Functions.

All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only.

The phase of one output group relative to the other can be adjusted through the SDA/SCL interface. For post-divide ratios (P0, P1) that are multiples of 5, the total number of phase adjustment steps (η) equals the divide-ratio divided by 5. For post-divide ratios (P0, P1) that are not multiples of 5, the total number of steps (η) is the same as the post-divide ratio. The phase adjustment step (ΔΦ) in time units is given as: ΔΦ = 1/(n?×?FOUT), where FOUT is the respective output frequency.

The device operates in a 1.8-V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810RGZT is available in a 48-pin VQFN (RGZ) package.

Feature

  • Single 1.8-V Supply
  • High-Performance Clock Distributor with 10 Outputs
  • Low Input-to-Output Additive Jitter: as Low as 10fs RMS
  • Output Group Phase Adjustment
  • Low-Voltage Differential Signaling (LVDS) Input, 100-Ω Differential On-Chip Termination, up to 650 MHz Frequency
  • Differential Current Mode Logic (CML) Outputs, 50-Ω Single-Ended On-Chip Termination, up to 650 MHz Frequency
  • Two Groups of Five Outputs Each with Independent Frequency Division Ratios
  • Output Frequency Derived with Divide Ratios of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80
  • Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements
  • Power Consumption: 410 mW Typical
  • Output Enable Control for Each Output and Automatic Output Synchronization
  • SDA/SCL Device Management Interface
  • 48-pin VQFN (RGZ) Package
  • Industrial Temperature Range: –40°C to +85°C


CDCL1810RGZT所属分类:时钟缓冲器/驱动器芯片,CDCL1810RGZT 由 德州仪器 (Texas) 设计生产,可通过久芯网进行购买。CDCL1810RGZT价格参考¥55.118469,你可以下载 CDCL1810RGZT中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询CDCL1810RGZT规格参数、现货库存、封装信息等信息!

德州仪器 (Texas)

德州仪器 (Texas)

德州仪器公司(TI)是一家开发模拟IC和嵌入式处理器的全球半导体设计和制造公司。通过雇用世界上最聪明的人,TI创造了塑造技术未来的创新。如今,TI正在帮助超过10万名客户改变未来。

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