The LTC6950CUHH#PBF is a low phase noise integer-N frequency synthesizer core with clock distribution. The LTC6950CUHH#PBF delivers the low phase noise clock signals demanded in high frequency, high resolution data acquisition systems.
The frequency synthesizer contains a full low noise PLL core with a programmable reference divider (R), a programmable feedback divider (N), a phase/frequency detector (PFD) and a low noise charge pump (CP). The clock distribution section of the LTC6950CUHH#PBF delivers up to five outputs based on the VCO input. Each output is individually programmed to divide the VCO input frequency by any integer from 1 to 63 and to delay the output by 0 to 63 VCO clock cycles. Four of the outputs feature very low noise, low skew LVPECL logic signals capable of operation up to 1.4GHz. The fifth output is selectable as either an LVDS (800MHz) or CMOS (250MHz) logic type. This output is also programmed to produce an output signal based on either the VCO input or the reference divider output.
Feature
- Low Phase Noise and Jitter
- Additive Jitter: 18fsRMS (12kHz to 20MHz)
- Additive Jitter: 85fsRMS (10Hz to Nyquist)
- EZSync™ Multichip Clock Edge Synchronization
- Full PLL Core with Lock Indicator
- –226dBc/Hz Normalized In-Band Phase Noise Floor
- –274dBc/Hz Normalized 1/f Phase Noise
- 1.4GHz Maximum VCO Input Frequency
- Four Independent, Low Noise 1.4GHz LVPECL Outputs
- One LVDS/CMOS Configurable Output
- Five Independently Programmable Dividers Covering All Integers from 1 to 63
- Five Independently Programmable VCO Clock Cycle Delays Covering All Integers from 0 to 63
- –40°C to 105°C Junction Temperature Range
Applications
- Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems
- Low Jitter Clock Generation and Distribution
