The AD9520-0BCPZ-REEL7 provides a multi-output clock distributionfunction with subpicosecond jitter performance, along with anon-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHzto 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHzcan also be used.
The AD9520-0BCPZ-REEL7 serial interface supports both SPI and I²C ports.An in-package EEPROM, which can be programmed through theserial interface, can store user-defined register settings forpower-up and chip reset.
The AD9520-0BCPZ-REEL7 features 12 LVPECL outputs in four groups. Anyof the 1.6 GHz LVPECL outputs can be reconfigured as two250 MHz CMOS outputs. If an application requires LVDSdrivers instead of LVPECL drivers, refer to the AD9522-0.
Each group of three outputs has a divider that allows both thedivide ratio (from 1 to 32) and the phase offset or coarse timedelay to be set.
The AD9520-0BCPZ-REEL7 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. The external VCO can have anoperating voltage of up to 5.5 V. A separate output driver powersupply can be from 2.375 V to 3.465 V.
The AD9520-0BCPZ-REEL7 is specified for operation over the standardindustrial range of −40°C to +85°C.
Feature
- Low phase noise, phase-locked loop (PLL)
- On-chip VCO tunes from 2.53 GHz to 2.95 GHz
- Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
- 1 differential or 2 single-ended reference inputs
- Accepts CMOS, LVDS, or LVPECL references to 250 MHz
- Accepts 16.62 MHz to 33.3 MHz crystal for reference input
- Optional reference clock doubler
- Reference monitoring capability
- Automatic/manual reference holdover and reference switchover modes, with revertive switching
- Glitch-free switchover between references
- Automatic recovery from holdover
- Digital or analog lock detect, selectable
- Optional zero delay operation
- Twelve 1.6 GHz LVPECL outputs divided into 4 groups
- Each group of 3 outputs shares a 1-to-32 divider with phase delay
- Additive output jitter as low as 225 fs rms
- Channel-to-channel skew grouped outputs < 16 ps
- Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz)
- Automatic synchronization of all outputs on power-up
- Manual output synchronization available
- SPI- and I2C-compatible serial control port
- 64-lead LFCSP
- Nonvolatile EEPROM stores configuration settings
Applications
- Low jitter, low phase noise clock distribution
- Clock generation and translation for SONET, 10Ge, 10GFC,Synchronous Ethernet, OTU2/3/4
- Forward error correction (G.710)
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- High performance wireless transceivers
- ATE and high performance instrumentation
- Broadband infrastructures
(Picture: Pinout)
