The Flash*Freeze technology used in IGLOO PLUS devices enables entering and exiting an ultralow-power mode that consumes as little as 5 µW while retaining the design information, SRAM content, registers, and I/O states. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode.
The Low Power Active capability (static idle) allows for ultra-low-power consumption while the IGLOO PLUS device is completely functional in the system. This allows the IGLOO PLUS device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power.
Nonvolatile flash technology gives IGLOO PLUS devices the advantage of being a secure, lowpower, single-chip solution that is live at power-up (LAPU). IGLOO PLUS is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.
IGLOO PLUS devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). IGLOO PLUS devices have up to 125 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 212 user I/Os. The AGLP030 devices have no PLL or RAM support.
Feature
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content
• Configurable Hold Previous State, Tristate, HIGH, or LOW State per I/O in Flash*Freeze Mode
• Up to 36 kbits of True Dual-Port SRAM
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• FlashLock® to Secure FPGA Contents
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content
• Configurable Hold Previous State, Tristate, HIGH, or LOW State per I/O in Flash*Freeze Mode
• Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode
Feature Rich
• 30 k to 125 k System Gates• Up to 36 kbits of True Dual-Port SRAM
• Up to 212 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)†• FlashLock® to Secure FPGA Contents
