Feature
• LP/Sleep Mode for Additional Power Savings
• Advanced Small-Footprint Packages
• Hot-Swap Compliant I/Os
• Single-Chip Solution
• Nonvolatile
• Live on Power-Up
• No Power-Up/Down Sequence Required for Supply Voltages
• Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during Power-Up
• Individual Output Slew Rate Control
• 2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength
• Software Design Support with Microsemi Designer and Libero® Integrated Design Environment (IDE) Tools
• Up to 100% Resource Utilization with 100% Pin Locking
• Deterministic Timing
• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG)
• Fuselock™ Secure Programming Technology Designed to Prevent Reverse Engineering and Design Theft
