Feature
• 66 MHz PCI
• CPLD and FPGA Integration
• Single-Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse Engineering and Design Theft
• CPLD and FPGA Integration
• Single-Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse Engineering and Design Theft
