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LFXP6C-3TN144C

  • 描述:电源电压: 1.71V ~ 3.465V 供应商设备包装: 144-TQFP(20x20) 工作温度: 0摄氏度~85摄氏度(TJ) 安装类别: 表面安装
  • 品牌: 莱迪思 (Lattice)
  • 交期:5-7 工作日
渠道:
  • 自营
  • 得捷
  • 贸泽

起订量: 1

  • 库存: 0
  • 单价: ¥3,489.61473
  • 数量:
    - +
  • 总计: ¥3,489.61
在线询价

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规格参数

  • 制造厂商 莱迪思 (Lattice)
  • 逻辑阵列块/可配置逻辑块数量 -
  • 闸门数量 -
  • 安装类别 表面安装
  • 工作温度 0摄氏度~85摄氏度(TJ)
  • 包装/外壳 144磅/平方英尺
  • 供应商设备包装 144-TQFP(20x20)
  • 输入/输出数量 100
  • 电源电压 1.71V ~ 3.465V
  • RAM 总位数 73728
  • 部件状态 过时的
  • 逻辑元件/单元的数量 6000

LFXP6C-3TN144C 产品详情

The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs. 

The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXP™ technology. With this technology, expensive external configuration memories are not required and designs are secured from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications. 

The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the LatticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and backannotates it into the design for timing verification. 

Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.

Feature

■ Non-volatile, Infinitely Reconfigurable 

• Instant-on 

– powers up in microseconds 

• No external configuration memory 

• Excellent design security, no bit stream to intercept 

• Reconfigure SRAM based logic in milliseconds 

• SRAM and non-volatile memory programmable through system configuration and JTAG ports 

■ Sleep Mode 

• Allows up to 1000x static current reduction 

■ TransFR™ Reconfiguration (TFR) 

• In-field logic update while system operates 

■ Extensive Density and Package Options 

• 3.1K to 19.7K LUT4s 

• 62 to 340 I/Os 

• Density migration supported 

■ Embedded and Distributed Memory 

• 54 Kbits to 396 Kbits sysMEM™ Embedded Block RAM 

• Up to 79 Kbits distributed RAM 

• Flexible memory resources: − Distributed and block memory 

■ Flexible I/O Buffer 

• Programmable sysIO™ buffer supports wide range of interfaces: 

− LVCMOS 3.3/2.5/1.8/1.5/1.2 

− LVTTL 

– SSTL 18 Class I 

− SSTL 3/2 Class I, II 

– HSTL15 Class I, III 

− HSTL 18 Class I, II, III 

− PCI 

− LVDS, Bus-LVDS, LVPECL, RSDS 

■ Dedicated DDR Memory Support 

• Implements interface up to DDR333 (166MHz) 

■ sysCLOCK™ PLLs 

• Up to 4 analog PLLs per device 

• Clock multiply, divide and phase shifting 

■ System Level Support 

• IEEE Standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability 

• Onboard oscillator for configuration 

• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply


LFXP6C-3TN144C所属分类:现场可编程门阵列(FPGA),LFXP6C-3TN144C 由 莱迪思 (Lattice) 设计生产,可通过久芯网进行购买。LFXP6C-3TN144C价格参考¥3489.614734,你可以下载 LFXP6C-3TN144C中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询LFXP6C-3TN144C规格参数、现货库存、封装信息等信息!

莱迪思 (Lattice)

莱迪思 (Lattice)

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