power FPGAs in the marketplace.
Stratix III FPGAs lower power consumption through Altera’s innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption for blocks not in use. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry’s lowest power, high-performance FPGAs.
Specifically designed for ease of use and rapid system integration, the Stratix III FPGA family offers two variants optimized to meet different application needs: ■ The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications. ■ The Stratix III E family is memory- and multiplier-rich for data-centric applications.
Feature
Stratix III devices offer the following features:
■ 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers
■ High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity
■ Programmable Power Technology, which minimizes power while maximizing device performance
