By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz, balancing power consumption and processing speed.
Feature
- Advanced RISC architecture
- 131 Powerful instructions
- Fully static operation
- Up to 20MIPS throughput at 20MHz
- On-chip 2-cycle multiplier
- High endurance non-volatile memory segments
- Optional boot code section with independent lock bits
- In-system programming by on-chip boot program
- True Read-While-Write operation
- Programming lock for software security
- Power-on reset and programmable brown-out detection
- Internal calibrated oscillator
