Feature
- Harvard architecture - parallel data and code access
- 3-Stage pipeline
- 32-bit Wide instruction and data bus
- 32-bit ALU
- 24-bit Addressing (16MB linear address space)
- Background debug controller (BDC)
- 2KB EEPROM with ECC
- Phase locked loop (IPLL) frequency multiplier with internal filter
- 1MHz Internal RC oscillator with +/-1.3% accuracy
- 4-20MHz Amplitude controlled pierce oscillator
- 32KHz Oscillator for RTC and LCD
- Internal COP (watchdog) module
- LCD driver for segment LCD with 40 frontplanes x 4 backplanes
- Stepper motor controller (MC) with drivers for up to 2 motors
- 2 Stepper stall detector (SSD) modules (one for each motor)
- RTC support the Hour/Minute/Second function and frequency compensation
- ADC with 10-bit resolution and up to 8 channels available on external pins
- 2 Timer module (TIM) - 16-bit input capture & output compare (8 channels)
- Pulse width modulation (PWM) modules with up to 8 x 8-bit channels
- Simple sound generation (SSG) for monotonic tone generation
Applications
Automotive, Motor Drive & Control, Communications & Networking, Industrial
