The SN65DSI86/96 DSI to embedded DisplayPort(eDP) bridge features a dual-channel MIPI D-PHY
receiver front-end configuration with 4 lanes per channel operating at 1.5Gbps per lane;
a maximum input bandwidth of 12Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 24bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, or 5.4Gbps.