Description：
The SN74AHC125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Features:
▄ Qualified for Automotive Applications
▄ ESD Protection Exceeds 1000 V Per
MIL-STD-883, Method 3015; Exceeds 150 V
Using Machine Model (C = 200 pF, R = 0)
▄ EPIC (Enhanced-Performance Implanted
CMOS) Process
▄ Operating Range 2-V to 5.5-V VCC
▄ Latch-Up Performance Exceeds 250 mA Per
JESD 17
Feature
- Qualified for Automotive Applications
- ESD Protection Exceeds 1000 V Per MIL-STD-883, Method 3015; Exceeds 150 V Using Machine Model (C = 200 pF, R = 0)
- EPIC? (Enhanced-Performance Implanted CMOS) Process
- Operating Range 2-V to 5.5-V VCC
- Latch-Up Performance Exceeds 250 mA Per JESD 17
EPICis a trademark of
(Picture:Pinout / Diagram)
