The SN74LVC126ADRE4 device is a quadruple bus buffer gate designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC126ADRE4 device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment.
Feature
- Operates From 1.65 V to 3.6 V
- Specified From –40°C to +125°C
- Inputs Accept Voltages up to 5.5 V
- Maximum tpd of 4.7 ns at 3.3 V
- Typical VOLP (Output Ground Bounce), <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot), >2 V at VCC = 3.3 V, TA = 25°C
- Latch-Up Performance Exceeds 250 mA Per JESD 17
The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment.
