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SN74LVCH16543ADLR

  • 描述:逻辑类型: 收发器,非反相 电源电压: 1.65伏~3.6伏 每个元件的位数: 8 供应商设备包装: 56-SSOP 工作温度: -40摄氏度~85摄氏度(TA) 安装类别: 表面安装
  • 品牌: 德州仪器 (Texas)
  • 交期:5-7 工作日
渠道:
  • 自营
  • 得捷
  • 贸泽

起订量: 226

  • 库存: 7896
  • 单价: ¥9.63306
  • 数量:
    - +
  • 总计: ¥2,177.07
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规格参数

  • 制造厂商 德州仪器 (Texas)
  • 部件状态 可供货
  • 逻辑类型 收发器,非反相
  • 元件数量 two
  • 每个元件的位数 8
  • 输入类别 -
  • 输出类别 三态
  • 工作温度 -40摄氏度~85摄氏度(TA)
  • 安装类别 表面安装
  • 输出高电流, 输出低电流 24毫安, 24毫安
  • 电源电压 1.65伏~3.6伏
  • 包装/外壳 56-BSSOP (0.295", 7.50毫米 Width)
  • 供应商设备包装 56-SSOP

SN74LVCH16543ADLR 产品详情

Widebus is a trademark of Texas Instruments.

Description

This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCH16543ADLR can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register, to permit independent control in either direction of data flow.

The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA\, LEBA\, and OEBA\ inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE\ or DIR.

Feature

  • Member of the Texas Instruments Widebus? Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.4 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

Description

This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCH16543A can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register, to permit independent control in either direction of data flow.

The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA\, LEBA\, and OEBA\ inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE\ or DIR.

SN74LVCH16543ADLR所属分类:逻辑接收/发送/驱动/缓冲器,SN74LVCH16543ADLR 由 德州仪器 (Texas) 设计生产,可通过久芯网进行购买。SN74LVCH16543ADLR价格参考¥9.633057,你可以下载 SN74LVCH16543ADLR中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询SN74LVCH16543ADLR规格参数、现货库存、封装信息等信息!

德州仪器 (Texas)

德州仪器 (Texas)

德州仪器公司(TI)是一家开发模拟IC和嵌入式处理器的全球半导体设计和制造公司。通过雇用世界上最聪明的人,TI创造了塑造技术未来的创新。如今,TI正在帮助超过10万名客户改变未来。

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