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SN74LVC821ADBR

  • 描述:种类: d型 电源电压: 1.65伏~3.6伏 每个元件的位数: ten 供应商设备包装: 24-SSOP 工作温度: -40摄氏度~85摄氏度(TA) 安装类别: 表面安装
  • 品牌: 德州仪器 (Texas)
  • 交期:2-3 工作日
渠道:
  • 自营
  • 得捷
  • 贸泽

起订量: 484

  • 库存: 12527
  • 单价: ¥12.51675
  • 数量:
    - +
  • 总计: ¥6,058.11
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规格参数

  • 制造厂商 德州仪器 (Texas)
  • 部件状态 可供货
  • 功能 标准
  • 种类 d型
  • 输出类别 三态,非反相
  • 元件数量 one
  • 正反器类别 上升沿
  • 工作温度 -40摄氏度~85摄氏度(TA)
  • 安装类别 表面安装
  • 输出高电流, 输出低电流 24毫安, 24毫安
  • 静态电流 (Iq) 10A.
  • 输入电容值 5 pF
  • 时钟频率 150兆赫
  • 电源电压 1.65伏~3.6伏
  • 每个元件的位数 ten
  • 最大传播延迟 @ 电压(V), 最大负载电容(CL) 7.3ns @ 3.3V, 50皮法
  • 供应商设备包装 24-SSOP
  • 包装/外壳 24-SSOP(0.209“,5.30毫米宽)

SN74LVC821ADBR 产品详情

This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC821ADBR features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Feature

  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 7.3 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
Description

This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74LVC821ADBR所属分类:触发器,SN74LVC821ADBR 由 德州仪器 (Texas) 设计生产,可通过久芯网进行购买。SN74LVC821ADBR价格参考¥12.516752,你可以下载 SN74LVC821ADBR中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询SN74LVC821ADBR规格参数、现货库存、封装信息等信息!

德州仪器 (Texas)

德州仪器 (Texas)

德州仪器公司(TI)是一家开发模拟IC和嵌入式处理器的全球半导体设计和制造公司。通过雇用世界上最聪明的人,TI创造了塑造技术未来的创新。如今,TI正在帮助超过10万名客户改变未来。

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