The SNx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Feature
- Wide Operating Voltage Range: 2 V to 6 V
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 40-μA Maximum ICC
- Typical tpd = 15 ns
- ±4-mA Output Drive at 5 V
- Very Low Input Current of 1 μA
The SNx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
