Feature
- Standard configuration
- Data can be continuously read from one bank while executing erase/program functions in another bank
- Zero latency between read and write operations
- Flexible bank architecture
- Read may occur in any of the three banks not being programmed or erased
- Four banks may be grouped by customer to achieve desired bank divisions
- Top and bottom boot sectors in the same device
- Any combination of sectors can be erased
- Manufactured on 0.11µm process technology
- Secured silicon region - Extra 256-byte sector
- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero
- Compatible with JEDEC standards
- Pinout and software compatible with single-power-supply flash standard
- High performance
- Program time - 7µs/word typical using accelerated programming function
- Ultralow power consumption
- Cycling endurance - 1million cycles per sector typical
- Data retention - 20 years typical
- Supports common flash memory interface
- Erase suspend/erase resume