High-performance 1-megabit EEPROM offers access times to 120ns with power dissipation of 220 m ( 440mW military). Deselected, CMOS standby current is less than 200µA (300µA military). It is accessed like static RAM for the read or write cycle without external components. It contains a 128-byte page register to allow writing of up to 128bytes simultaneously. The EEPROM features Internal error correction for extended endurance and improved data retention. Optional software data protection mechanism guards against inadvertent writes, and an extra 128 bytes of EEPROM enables device identification or tracking.
Feature
• Fast Read Access Time - 120 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 128-Bytes
– Internal Control Timer
• Fast Write Cycle Time
– Page Write Cycle Time - 10 ms Maximum
– 1 to 128-Byte Page Write Operation
• Low Power Dissipation
– 80 mA Active Current
– 300 µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
• Single 5V 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-Wide Pinout
Description
The AT28C010 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its one megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 300uA.
The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128- bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.
Atmel's 28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128-bytes of EEPROM for device identification or tracking.
(Picture: Pinout)
