·Wide Operating Voltage Range of2V to 6V
·Outputs Can Drive Up To 10 LSTTL Loads
·Low Power Consumption,80-uA Max lcc
·Typical tpd=13 ns
·±4-mA Output Drive at 5V
·Low Input Current of 1 uA Max
·Single Down/Up Count-Control Line
·Look-Ahead Circuitry Enhances Speed of Cascaded Counters
·Fully Synchronous in Count Modes
·Asynchronously Presettable With Load Control
description/ordering information
The HC191 devices are 4-bit synchronous, reversible, up/down binary counters.Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous
(ripple-clock) counters.
The outputs of the four flip-flops are triggered on a low-to high-level transition of the clock(CLK)input if the count-enable (CTEN) input is low.A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up(D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down.
description/ordering information(continued)
These counters feature a fully independent clock circuit. Change at the control (CTEN and D/) inputs that modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, each of the outputs can be preset to either level by placing alow on the load(LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independenty of the level of CLK. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs.
Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum
(MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero(all outputs low) counting down, or maximum (9 or 15)
counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low.
The counters can be cascaded easily by feeding RCO to CTEN of the succeeding counter if parallel clocking is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed operation.
Feature
- Synchronous reversible counting
- Count enable control for synchronous expansion
- Single up/down control input
- Standard Output capability
- ICC Category
(Picture: Pinout)
