The CY7C4255/65 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
Feature
• High-speed, low-power, first-in first-out (FIFO) memories
• 8K x 18 (CY7C4255)
• 16K x 18 (CY7C4265)
• 0.5 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10 ns read/write cycle times)
• Low power — ICC = 45 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags
• TTL compatible
• Retransmit function
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin PLCC, 64-pin TQFP and 64-pin STQFP
• Pin-compatible density upgrade to CY7C42X5 family
• Pin-compatible density upgrade to IDT72205/15/25/35/45
