The SY100EL32VZI is an integrated divide by 4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The Reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state. The Reset allows for the synchronization of multiple EL32Vs in a system.
Feature
■ 3.3V and 5V power supply options
■ 510ps propagation delay
■ 3.0GHz toggle frequency
■ High bandwidth output transistions
■ Internal 75KΩ input pull-down resistors
■ Available in 8-pin SOIC package
