The 723623L12PFG is a 256 x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers.
Feature
- IDT Standard timing or First Word Fall Through Timing
- Programmable Almost-Empty and Almost-Full flags
- Serial or parallel programming of partial flags
- Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)
- Big- or Little-Endian format for word and byte bus sizes
- Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
- Mailbox bypass registers for each FIFO
- Easily expandable in width and depth
- Auto power down minimizes power dissipation
- Available in 128-pin TQFP package
