The 7206L50J is a 16K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
Feature
- Pin and functionally compatible with 720X family
- Low power consumption
- Ultra high speed—12ns access time
- Asynchronous and simultaneous read and write
- Fully expandable by both word depth and/or bit width
- Status Flags: Empty, Half-Full, Full
- Auto-retransmit capability
- MIL-STD-883, Class B available in 28 pin (600 mil) Cerdip and 32 pin LCC packages
- Industrial temperature range (–40C to +85C) is available
- Available in 28 pin PDIP (300 & 600 mil), and 32 pin PLCC packages
