Description:
CD4026B and CD4033BE each con-sist of a 5stage Johnson decade counter and an output decoder which converts theJohnson code to a 7-segment decoded out-put for driving one stage in a numerical display.
These devices are particulerly advantageous in display applications where low power dissipation. and/or low package count are important.Inputs common to both types are CLOCK, RESET,& CLOCK INHiBIT; common outputs are CARRY OUT and the seven decoded outputs (a,b,c,d,e,f,g). Addi-tional inputs and outputs for the CD40268
include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C.
SEGMENT"outputs. Signals peculiar to the CD4033BE are RIPPLE-BLANKING INPUTAND LAMP TEST INPUT and a RIPPLE-
BLANKING OUTPUT.
A high RESET signal clears the decade counter to its zero count. The counter isadvanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCKINHIBIT signal is high. The CLOCK INHI-BIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT(Cut) signal completes one cycle every ten CLOCK INPUT cycles and is used 1o clock the succeeding decade di-rectly in a multi-decade counting chain.
The seven decoded outputs (a,b,c,d,e,f,g) illuminate the proper segments in a seven
Features:
· Counter and 7-tegment decoding in one packageEatily interfaced with 7-segment display types Fully static counter
operation: DC to 6 MHz (typ.) at Vpp=10V
· Ideal for low-power displays
· Display enable output { CD4026B)"Ripple blanking"and lamp test (CD4033B)
· 100% tested for quiescent current at 20V
· Standardized, symmetrical output characteristics 5-V,10V, and 15-V parametric ratings
· Schmitt-triggered clock inputs
· Meets all requirements of JEDEC Tentative Standard No.13B,"Standard Specifications for Description of B' Saries CMOS Devices"
Feature
Description:
CD4026B and CD4033B each con-sist of a 5stage Johnson decade counter and an output decoder which converts theJohnson code to a 7-segment decoded out-put for driving one stage in a numerical display.
These devices are particulerly advantageous in display applications where low power dissipation. and/or low package count are important.Inputs common to both types are CLOCK, RESET,& CLOCK INHiBIT; common outputs are CARRY OUT and the seven decoded outputs (a,b,c,d,e,f,g). Addi-tional inputs and outputs for the CD40268
include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C.
SEGMENT"outputs. Signals peculiar to the CD4033B are RIPPLE-BLANKING INPUTAND LAMP TEST INPUT and a RIPPLE-
BLANKING OUTPUT.
A high RESET signal clears the decade counter to its zero count. The counter isadvanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCKINHIBIT signal is high. The CLOCK INHI-BIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT(Cut) signal completes one cycle every ten CLOCK INPUT cycles and is used 1o clock the succeeding decade di-rectly in a multi-decade counting chain.
The seven decoded outputs (a,b,c,d,e,f,g) illuminate the proper segments in a seven
Features:
· Counter and 7-tegment decoding in one packageEatily interfaced with 7-segment display types Fully static counter
operation: DC to 6 MHz (typ.) at Vpp=10V
· Ideal for low-power displays
· Display enable output { CD4026B)"Ripple blanking"and lamp test (CD4033B)
· 100% tested for quiescent current at 20V
· Standardized, symmetrical output characteristics 5-V,10V, and 15-V parametric ratings
· Schmitt-triggered clock inputs
· Meets all requirements of JEDEC Tentative Standard No.13B,"Standard Specifications for Description of B' Saries CMOS Devices"
Applications
(Picture: Pinout)
