The IDT72V2103/72V2113 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x9/x18 data flow. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following:
• Flexible x9/x18 Bus-Matching on both read and write ports.
• The limitation of the frequency of one clock input with respect to the other has been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)
• Asynchronous/Synchronous translation on the read or write ports.
• High density offerings up to 4 Mbit.
Bus-Matching SuperSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.
FEATURES
• Choose among the following memory organizations:
- IDT72V2103 ⎯ 131,072 x 18/262,144 x 9
- IDT72V2113 ⎯ 262,144 x 18/524,288 x 9
• Functionally compatible with the IDT72V255LA/72V265LA and IDT72V275/72V285 SuperSync FIFOs
• Up to 166 MHz Operation of the Clocks
• User selectable Asynchronous read and/or write ports (BGA Only)
• 6 ns read/write cycle time (4.0 ns access time)
• User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V tolerant inputs
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (BGA Only)
• Independent Read and Write Clocks (permit reading and writing simultaneously)
• Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball Grid Array (BGA) (with additional features)
• Pin compatible to the SuperSync II (IDT72V223/72V233/72V243/ 72V253/72V263/72V273/72V283/72V293) family
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
Feature
- 10 ns read/write cycle time
- 5V input tolerant
- Read and Write clocks can be independent
- Dual-Ported zero fall-through time architecture
- Empty and Full Flags signal FIFO status
- Programmable Almost-Empty and Almost-Full flags can be set to any depth
- Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively
- Output Enable puts output data bus in high-impedance state
- Available in 32-pin PLCC and TQFP packages
- Industrial temperature range (–40C to +85C) is available
