The 74ACT11623DW is designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timing.
The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the enable inputs (G\BA and GAB). The enable inputs can be used to disable the device so that the buses are effectively isolated.
The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of G\BA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical for the 74ACT11623.
The 74ACT11623DW is characterized for operation from - 40°C to 85°C.
Feature
- Local Bus-Latch Capability
- Inputs Are TTL-Voltage Compatible
- Flow-Through Architecture Optimizes PCB Layout
- Center-Pin VCC and GND Configurations MinimizeHigh-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Small- Outline Packages andStandard Plastic 300-mil DIPs
