This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
NanoFree? package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A low level at the preset (CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Feature
- Available in the Texas Instruments NanoFree? Package
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.9 ns at 3.3 V
- Low Power Consumption, 10-μA Max ICC
- ±24-mA Output Drive at 3.3 V
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
- Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model
- 200-V Machine Model
- 1000-V Charged-Device Model
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
NanoFree? package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A low level at the preset (CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
