Features
• Operating Range 2-V to 5.5-V Vcc
• Contain Eight Flip-Flops With Single-Rail Outputs
• Direct Clear Input
• Individual Data Input to Each Flip-Flop
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
-2000-VHuman-Body Model(A114-A)
-1000-V Charged-Device Model(C101)
• On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
Applications
• Buffers and Storage Registers
• Shift Registers
• Pattern Generators
• Servers
• PCs and Notebooks
• Network Switches
• Memory Systems
• Databases
Description
These devices are positive-edge-triggered D-type flip-flops with a direct clear(CLR) input.
Information at the data(D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock(CLK) pulse.
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
Feature
- Operating Range 2-V to 5.5-V VCC
- Contain Eight Flip-Flops With Single-Rail Outputs
- Direct Clear Input
- Individual Data Input to Each Flip-Flop
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
- On Products Compliant to MIL-PRF-38535,All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
These devices are positive-edge-triggered D-typeflip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
(Picture:Pinout / Diagram)
