Description
These monolithic, positive-edge-triggered flip-flopsutilize TTL circuitry to implement D-type flip-flop logic with an enable input. The ' LS377,' LS378, and LS379 devices are similar to ' LS273,' LS174, andLS175, respectively, but feature a common enable instead of a common clear.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enableinput is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When theclock input is at either the high or low level, the D input signal has no effect at the output. The circuitsare designed to prevent false clocking by transitions at the G input.These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz.
Typical power dissipation is 10 milliwatts per flip-flop.
·'LS377 and'LS378 Contain Eight and Six Flip-Flops,Respectively,with Single-Rail Outputs
·'LS379 Contains Four Flip-Flops with Double-Rail Outputs
·Individual Data Input to Each Flip-Flop
·Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators
Feature
- 'LS377 and 'LS378 Contain Eight and Six Flip-Flops, Respectively, with Single-Rail Outputs
- 'LS379 Contains Four Flip-Flops with Double-Rail Outputs
- Individual Data Input to Each Flip-Flop
- Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input.
These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
(Picture: Pinout)
