The SY10EP51VKC is a D flip-flop with reset anddifferential clock. The device is pin and functionally equivalent to the EL51device.The reset input is an asynchronous, level triggered signal. Data entersthe master portion of the flip-flop when CLK is LOW and is transferred to theslave, and thus the outputs, upon a positive transition of the CLK. Thedifferential clock inputs of the EP51V allow the device to be used as anegative edge triggered flip-flop.The differential input employs clampcircuitry to maintain stability under open input conditions. When left open,the CLK input will be pulled down to VEE and the /CLK input will be biaseda VCC/2.
Feature
■ 3.3V and 5V power supply options
■ 320ps typical propagation delay
■ Maximum frequency > 3GHz typical
■ 75KΩ internal input pulldown resistor
■ Transistor count: 143
■ Available in 8-Pin (3mmx3mm) MSOP, SOIC and MLF® (2mmx2mm) packages
