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SN74AS867DWR

  • 描述:逻辑类型: 二进制计数器 电源电压: 4.5 V ~ 5.5 V 每个元件的位数: 8 计数速度率: 50 MHz 供应商设备包装: 24-SOIC 安装类别: 表面安装
  • 品牌: 德州仪器 (Texas)
  • 交期:5-7 工作日
渠道:
  • 自营
  • 得捷
  • 贸泽

起订量: 46

  • 库存: 180
  • 单价: ¥47.58585
  • 数量:
    - +
  • 总计: ¥2,188.95
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规格参数

  • 部件状态 过时的
  • 逻辑类型 二进制计数器
  • 元件数量 one
  • 电源电压 4.5 V ~ 5.5 V
  • 重置 异步
  • 定时 同步的
  • 正反器类别 上升沿
  • 安装类别 表面安装
  • 制造厂商 德州仪器 (Texas)
  • 工作温度 0摄氏度~70摄氏度
  • 定向 向上,向下
  • 计数速度率 50 MHz
  • 每个元件的位数 8
  • 包装/外壳 24-SOIC(0.295“,7.50毫米宽)
  • 供应商设备包装 24-SOIC

SN74AS867DWR 产品详情

These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (,) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform.

These counters are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters. Because loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Two count-enable (and ) inputs and a ripple-carry () output are instrumental in accomplishing this function. Bothand must be low to count. The direction of the count is determined by the levels of the select (S0, S1) inputs as shown in the function table. is fed forward to enable .thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages. Transitions atand are allowed regardless of the level of CLK. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design.

These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the SN74ALS867A and ′AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q outputs until clocking occurs. For the ′AS867 and ′AS869, any time ENP\ and/or ENT\ is taken high,either goes or remains high. For the SN74ALS867A and SN74ALS869, any time is taken high,either goes or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for operation from 0°C to 70°C.

Feature

  • Fully Programmable With Synchronous Counting and Loading
  • SN74ALS867A and ′AS867 Have Asynchronous Clear;SN74ALS869 and ′AS869 Have Synchronous Clear
  • Fully Independent Clock Circuit Simplifies Use
  • Ripple-Carry Output for n-Bit Cascading
  • Package Options Include Plastic Small-Outline (DW) Packages,Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic(JT) 300-mil DIPs
SN74AS867DWR所属分类:计数器/触发器芯片,SN74AS867DWR 由 德州仪器 (Texas) 设计生产,可通过久芯网进行购买。SN74AS867DWR价格参考¥47.585853,你可以下载 SN74AS867DWR中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询SN74AS867DWR规格参数、现货库存、封装信息等信息!

德州仪器 (Texas)

德州仪器 (Texas)

德州仪器公司(TI)是一家开发模拟IC和嵌入式处理器的全球半导体设计和制造公司。通过雇用世界上最聪明的人,TI创造了塑造技术未来的创新。如今,TI正在帮助超过10万名客户改变未来。

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