General Description
The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Features
■ Ideal buffer for MOS microprocessor or memory
■ Eight edge-triggered D-type flip-flops
■ Buffered common clock
■ Buffered, asynchronous Master Reset
■ See 74F377 for clock enable version
■ See 74F373 for transparent latch version
■ See 74F374 for 3-STATE version
(Picture: Pinout)
