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SN74AS374N-J
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SN74AS374N-J

渠道:
  • 自营
  • 得捷
  • 贸泽

起订量: 158

数量 单价 合计
158+ 13.76151 2174.31858
  • 库存: 8380
  • 单价: ¥13.76151
  • 数量:
    - +
  • 总计: ¥2,174.32
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规格参数

  • 制造厂商 德州仪器 (Texas)
  • 部件状态 可供货
  • 特点 -
  • 最大静态电流 -
  • 低逻辑电平 -
  • 高逻辑电平 -
  • 逻辑类型 -
  • 电线数量 -
  • 输入数量 -
  • 电源电压 -
  • 输出高电流, 输出低电流 -
  • 最大传播延迟 @ 电压(V), 最大负载电容(CL) -
  • 工作温度 -
  • 安装类别 -
  • 供应商设备包装 -
  • 包装/外壳 -

SN74AS374N-J 产品详情

These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS374A and SN74AS374N are characterized for operation from 0°C to 70°C.

Feature

  • D-Type Flip-Flops in a Single Package With 3-State Bus Driving True Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
Description

These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C.

SN74AS374N-J所属分类:逻辑门/反相器,SN74AS374N-J 由 德州仪器 (Texas) 设计生产,可通过久芯网进行购买。SN74AS374N-J价格参考¥13.761510,你可以下载 SN74AS374N-J中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询SN74AS374N-J规格参数、现货库存、封装信息等信息!

德州仪器 (Texas)

德州仪器 (Texas)

德州仪器公司(TI)是一家开发模拟IC和嵌入式处理器的全球半导体设计和制造公司。通过雇用世界上最聪明的人,TI创造了塑造技术未来的创新。如今,TI正在帮助超过10万名客户改变未来。

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