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CD4502BF
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CD4502BF

  • 描述:INVERTER/BUFFER
  • 品牌:
  • 交期:5-7 工作日
渠道:
  • 自营
  • 得捷
  • 贸泽

起订量: 1

  • 库存: 0
  • 单价: ¥12.16807
  • 数量:
    - +
  • 总计: ¥12.17
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规格参数

  • 输出高电流, 输出低电流 -
  • 部件状态 可供货
  • 逻辑类型 -
  • 电线数量 -
  • 输入数量 -
  • 施密特触发输入 -
  • 输出类别 -
  • 电源电压 -
  • 工作温度 -
  • 安装类别 -
  • 包装/外壳 -
  • 供应商设备包装 -
  • 制造厂商

CD4502BF 产品详情

CD4502BF consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE inputproduces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOL standard.

The CD4502BF types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Feature

  • 2 TTL-load output drive capability
  • 3-state outputs
  • Common output-disable control
  • Inhibit control
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Noise Margin (full package-temperature range) =
       1 V at VDD = 5 V
       2 V at VDD = 10 V
       2.5 V at VDD = 15 V
  • Applications:
    • 3-state hex inverter for interfacing IC's with data buses
    • COS/MOS to TTL hex buffer
CD4502BF所属分类:可配置多功能逻辑门芯片,CD4502BF 由 设计生产,可通过久芯网进行购买。CD4502BF价格参考¥12.168072,你可以下载 CD4502BF中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询CD4502BF规格参数、现货库存、封装信息等信息!
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