Data sheet acquired from Harris Semiconductor
DescriptionCD4071B, CD4072B and CD4075BPWR OR gates provide the system designer with direct implementation of the positive-logicOR function and supplement the existing family of CMOS gates.
The CD4071B, CD4072B, and CD4075BPWR types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix),14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-leadthin shrink small-outline packages (PW and PWR suffixes).
Feature
- Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Standardized, symmetrical output characteristics
- Noise margin (full package-temperature range): 1 V at VDD = 5 V 2 V at VDD = 10 V2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Data sheet acquired from Harris Semiconductor
DescriptionCD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logicOR function and supplement the existing family of CMOS gates.
The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix),14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-leadthin shrink small-outline packages (PW and PWR suffixes).
