This single 2-input positive-OR gate performs the Boolean function Y=A • B or Y=A + B in positive logic.
Features
• Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
• Low Static-Power Consumption (ICC = 0.9 µA Max)
• Low Dynamic-Power Consumption (Cpd = 4.3 pF Typ at 3.3 V)
• Low Input Capacitance (CI = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot <10% of VCC
•I off Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
• Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V)
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• t pd = 4.6 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model (A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Applications
• ATCA Solutions
• Active Noise Cancellation (ANC)
• Barcode Scanner the end of the datasheet.
• Blood Pressure Monitor
• CPAP Machine
• Cable Solutions
• DLP 3D Machine Vision, Hyperspectral Imaging,Optical Networking, and Spectroscopy
• E-Book
• Embedded PC
• Field Transmitter: Temperature or Pressure Sensor
• Fingerprint Biometrics
• HVAC: Heating, Ventilating, and Air Conditioning
• Network-Attached Storage (NAS)
• Server Motherboard and PSU
• Software Defined Radio (SDR)
• TV: High-Definition (HDTV), LCD, and Digital
• Video Communications System
• Wireless Data Access Card, Headset, Keyboard, Mouse, and LAN Card
• X-ray: Baggage Scanner, Medical, and Dental
Feature
- Available in the ultra-small 0.64 mm2 package (DPW) with0.5-mm pitch
- Low static-power consumption(ICC = 0.9 μA Max)
- Low dynamic-power consumption(Cpd = 4.3 pF Typ at 3.3 V)
- Low input capacitance (CI = 1.5 pF Typ)
- Low noise – overshoot and undershoot <10% of VCC
- Ioff Supports live insertion, partial-power-downmode, and back drive protection
- Input hysteresis allows slow input transition and better switching noise immunityat the input (Vhys = 250 mV typ at 3.3 V)
- Wide operating VCC range of 0.8 V to 3.6 V
- Optimized for 3.3-V operation
- 3.6-V I/O Tolerant to support mixed-mode signal operation
- tpd = 4.6 ns Max at 3.3 V
- Suitable for point-to-point applications
- Latch-up performance exceeds 100 mA Per JESD 78, Class II
- ESD performance tested Per JESD 22
- 2000-V Human-body model(A114-B, Class II)
- 1000-V Charged-device model (C101)
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DescriptionThis single 2-input positive-OR gate performs the Boolean functionin positive logic.
(Picture: Pinout)
