Low-Voltage CMOS logic
Operating Voltage: 2 to 5.5
Compatibility: Input LVTTL/TTL, Output LVCMOS
Feature
- 2-V to 5.5-V VCC Operation
- Max tpd of 7 ns at 5 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
