MC14099BFL1

The MC14094BDR2G(14094BG) combines an 8-stage shift register with a data latch for each stage and a three-state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QS output data is for use in high-speed cascaded systems. The Q S output data is shifted on the following negative clock transition for use in low-speed cascaded systems. Data from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high. Outputs of the eight data latches are controlled by three-state buffers which are placed in the high-impedance state by a logic Low on Output Enable.

Feature

(Picture: Pinout)