The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces. The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays.
Feature
Flexible Logic Resources
- Up to 93,184 internal registers / latches with Clock Enable
- Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and sum-of-products support
- Internal 3-state bussing
• High-Performance Clock Management Circuitry
- Up to 12 DCM (Digital Clock Manager) modules ·
Precise clock de-skew
· Flexible frequency synthesis
· High-resolution phase shifting
- 16 global clock multiplexer buffers
• Active Interconnect Technology
- Fourth generation segmented routing structure
- Predictable, fast routing delay, independent of fanout
• SelectIO™-Ultra Technology
- Up to 1,108 user I/Os
- 19 single-ended and six differential standards
- Programmable sink current (2 mA to 24 mA) per I/O
- Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards
