SN74AVC16373DGVR

  • 描述:逻辑类型: D型透明闩锁 集成电路: 8:8 电源电压: 1.4伏~3.6伏 输出类别: 三态 供应商设备包装: 48-TVSOP 安装类别: 表面安装
  • 品牌: 德州仪器 (Texas)
  • 交期:5-7 工作日
渠道:
  • 自营
  • 得捷
  • 贸泽

起订量: 2000

数量 单价 合计
2000+ 24.80512 49610.24400
  • 库存: 4000
  • 单价: ¥24.80512
  • 数量:
    - +
  • 总计: ¥49,610.24
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规格参数

  • 部件状态 可供货
  • 逻辑类型 D型透明闩锁
  • 集成电路 8:8
  • 输出类别 三态
  • 安装类别 表面安装
  • 制造厂商 德州仪器 (Texas)
  • 工作温度 -40摄氏度~85摄氏度
  • 独立电路板 two
  • 包装/外壳 48-TFSOP(0.173“,4.40毫米宽)
  • 供应商设备包装 48-TVSOP
  • 输出高电流, 输出低电流 12毫安, 12毫安
  • 电源电压 1.4伏~3.6伏
  • 延迟时间传播状态 7.2ns

SN74AVC16373DGVR 产品详情

2Widebus, EPIC, DOC are trademarks of Texas Instruments.

Description

A Dynamic Output Control (DOC?) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC?) Circuitry Technology and Applications, literature number SCEA009.

This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.

The SN74AVC16373DGVR is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16373DGVR is characterized for operation from –40°C to 85°C.

Feature

  • Member of the Texas Instruments Widebus? Family
  • EPIC? (Enhanced-Performance Implanted CMOS) Submicron Process
  • DOC? (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages

2Widebus, EPIC, DOC are trademarks of Texas Instruments.

Description

A Dynamic Output Control (DOC?) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC?) Circuitry Technology and Applications, literature number SCEA009.

This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.

The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16373 is characterized for operation from –40°C to 85°C.

SN74AVC16373DGVR所属分类:锁存器,SN74AVC16373DGVR 由 德州仪器 (Texas) 设计生产,可通过久芯网进行购买。SN74AVC16373DGVR价格参考¥24.805122,你可以下载 SN74AVC16373DGVR中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询SN74AVC16373DGVR规格参数、现货库存、封装信息等信息!

德州仪器 (Texas)

德州仪器 (Texas)

德州仪器公司(TI)是一家开发模拟IC和嵌入式处理器的全球半导体设计和制造公司。通过雇用世界上最聪明的人,TI创造了塑造技术未来的创新。如今,TI正在帮助超过10万名客户改变未来。

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