DESCRIPTION
The 74LCX573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the outputs will be in a high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
■ 5V TOLERANT INPUTS AND OUTPUTS
■ HIGH SPEED:tPD = 8.0 ns (MAX.) at VCC = 3V
■ POWER DOWN PROTECTION ON INPUTS AND OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:|IOH| = IOL = 24mA (MIN) at VCC = 3V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS:tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)
■ ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V
(Picture:Pinout / Diagram)
