EPIC is a trademark of Texas Instruments Incorporated.
DescriptionThe 74AC11138D circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select (A, B, C) inputs and the three enable (G1, , ) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The 74AC11138D is characterized for operation from -40°C to 85°C.
Feature
- Designed Specifically for High-Speed Memory Decoders and DataTransmission Systems
- Incorporates Three Enable Inputs to Simplify Cascading and/orData Reception
- Center-Pin VCC and GND Configurations MinimizeHigh-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Small-Outline (D) and ThinShrink Small-Outline (PW) Packages, and Standard Plastic 300-milDIPs (N)
EPIC is a trademark of Texas Instruments Incorporated.
DescriptionThe 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select (A, B, C) inputs and the three enable (G1, , ) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The 74AC11138 is characterized for operation from -40°C to 85°C.
