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SN74LV138ATRGYR

  • 描述:种类: 解码器/多路分解器 集成电路: 1 x 3:8 电源电压: 2伏~5.5伏 电压供应源: 单电源 供应商设备包装: 16-VQFN(4x3.5) 安装类别: 表面安装
  • 品牌: 德州仪器 (Texas)
  • 交期:5-7 工作日
渠道:
  • 自营
  • 得捷
  • 贸泽

起订量: 1777

数量 单价 合计
3000+ 1.39425 4182.77400
  • 库存: 26556
  • 单价: ¥1.23129
  • 数量:
    - +
  • 总计: ¥2,188.01
在线询价

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规格参数

  • 部件状态 可供货
  • 种类 解码器/多路分解器
  • 独立电路板 one
  • 电压供应源 单电源
  • 安装类别 表面安装
  • 工作温度 -40摄氏度~85摄氏度
  • 制造厂商 德州仪器 (Texas)
  • 输出高电流, 输出低电流 12毫安, 12毫安
  • 电源电压 2伏~5.5伏
  • 集成电路 1 x 3:8
  • 包装/外壳 16-VFQFN外露焊盘
  • 供应商设备包装 16-VQFN(4x3.5)

SN74LV138ATRGYR 产品详情

The SN74LV138ATRGYR is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

This device is fully specified for partial-power-down application susing Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Feature

  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V VCC Operation
  • Max tpd of 7.6 ns at 5 V
  • Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)>>2.3 V at VCC = 5 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
Description

The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

This device is fully specified for partial-power-down application susing Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

SN74LV138ATRGYR所属分类:信号开关/多路复用器/解码器,SN74LV138ATRGYR 由 德州仪器 (Texas) 设计生产,可通过久芯网进行购买。SN74LV138ATRGYR价格参考¥1.231293,你可以下载 SN74LV138ATRGYR中文资料、PDF数据手册、Datasheet数据手册功能说明书,可查询SN74LV138ATRGYR规格参数、现货库存、封装信息等信息!

德州仪器 (Texas)

德州仪器 (Texas)

德州仪器公司(TI)是一家开发模拟IC和嵌入式处理器的全球半导体设计和制造公司。通过雇用世界上最聪明的人,TI创造了塑造技术未来的创新。如今,TI正在帮助超过10万名客户改变未来。

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