The SN74SSQEA32882ZALR implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.
The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.
Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.
Feature
- JEDEC SSTE32882 Compliant
- 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs
- CKE Powerdown Mode for Optimized System Power Consumption
- 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and DCS[n:0]) are not part of this computation.
The SN74SSQEA32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.
The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.
Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.
