The SN74FB2033ARCR is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level A port. The common-I/O, open-collector B\ port operates at backplane transceiver logic (BTL) signal levels.
The logic element for data flow in each direction is configured by two mode inputs (IMODE1 and IMODE0 for B-to-A, OMODE1 and OMODE0 for A-to-B) as a buffer, a D-type flip-flop, or a D-type latch. When configured in the buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input (CLKAB/LEAB or CLKBA/LEBA). In the latch mode, the clock inputs serve as active-high transparent latch enables.
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the LOOPBACK input. When LOOPBACK is low, B\-port data is the B-to-A input. When LOOPBACK is high, the output of the selected A-to-B logic element (prior to inversion) is the B-to-A input.
The AO port-enable/-disable control is provided by OEA. When OEA is low or when VCC is less than 2.5 V, the AO port is in the high-impedance state. When OEA is high, the AO port is active (high or low logic levels).
The B\ port is controlled by OEB and OEB\. If OEB is low, OEB\ is high, or VCC is less than 2.5 V, the B\ port is inactive. If OEB is high and OEB\ is low, the B\ port is active.
BG VCC and BG GND are the bias-generator reference inputs.
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated outputs are in the high-impedance (AO port) or inactive (B\ port) states.
Output clamps are provided on the BTL outputs to reduce switching noise. One clamp reduces inductive ringing effects on VOH during a low-to-high transition. The other clamps out ringing below the BTL VOL voltage of 0.75 V. Both clamps are active only during ac switching and do not affect the BTL outputs during steady-state conditions.
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
Feature
- Compatible With IEEE Std 1194.1-1991 (BTL)
- TTL A Port, Backplane Transceiver Logic (BTL) B\ Port
- Open-Collector B\-Port Outputs Sink 100 mA
- BIAS VCC Pin Minimizes Signal Distortion During Live Insertion or Withdrawal
- High-Impedance State During Power Up and Power Down
- B\-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage
- TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination
