The CDC339NSR is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.
When the output-enable ( ) input is low and the clear () input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions of CLK. Takinglow asynchronously resets the Q outputs to the low level. Whenis high, the outputs are in the high-impedance state.
The CDC339NSR is characterized for operation from -40°C to 85°C.
Feature
- Low Output Skew, Low Pulse Skew for Clock-Distribution andClock-Generation Applications
- TTL-Compatible Inputs and Outputs
- Distributes One Clock Input to Eight Outputs
- Four Same-Frequency Outputs
- Four Half-Frequency Outputs
- Distributed VCC and Ground Pins Reduce SwitchingNoise
- High-Drive Outputs (-48-mA IOH, 48-mAIOL)
- State-of-the-Art EPIC-IIBTM BiCMOS DesignSignificantly Reduces Power Dissipation
- Package Options Include Plastic Small-Outline (DW) and ShrinkSmall-Outline (DB) Packages
