1FEATURES
• 2-Bit Bidirectional Translator for SDA and SCL Lines in Mixed-Mode I 2C Applications
• I 2C and SMBus Compatible
• Less Than 1.5-ns Maximum Propagation Delay to Accommodate Standard-Mode and Fast-Mode I 2C Devices and Multiple Masters
• Allows Voltage-Level Translator Between
– 1.2-V VREF1 and 1.8-V, 2.5-V, 3.3-V, or 5-V VREF2
– 1.8-V VREF1 and 2.5-V, 3.3-V, or 5-V VREF2
– 2.5-V VREF1 and 3.3-V or 5-V VREF2
– 3.3-V VREF1 and 5-V VREF2
• Provides Bidirectional Voltage Translation With No Direction Pin
• Low 3.5-Ω ON-State Connection Between Input and Output Ports Provides Less Signal Distortion
• Open-Drain I 2C I/O Ports (SCL1, SDA1, SCL2, and SDA2)
• 5-V Tolerant I 2C I/O Ports to Support Mixed-Mode Signal Operation
• High-Impedance SCL1, SDA1, SCL2, and SDA2 Pins for EN = Low
• Lock-Up-Free Operation for Isolation When EN = Low
• Flow-Through Pinout for Ease of Printed Circuit Board Trace Routing
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This dual bidirectional I 2C and SMBus voltage-level translator, with an enable (EN) input, is operational from 1.2-V to 3.3-V VREF1 and 1.8-V to 5.5-V VREF2.
The PCA9306DQER allows bidirectional voltage translations between 1.2 V and 5 V, without the use of a direction pin. The low ON-state resistance (ron) of the switch allows connections to be made with minimal propagation delay. When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and a high-impedance state exists between ports.
In I 2C applications, the bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9306DQER enables the system designer to isolate two halves of a bus; thus, more I 2C devices or longer trace length can be accommodated.
Feature
- 2-Bit bidirectional translator for SDA and SCL lines in mixed-modeI2C Applications
- I2C and SMBus Compatible
- Less than 1.5-ns Maximum Propagation Delay to Accommodate Standard-mode andFast-mode I2C Devices and Multiple Masters
- Allows Voltage-level Translation Between
- 1.2-V VREF1 and 1.8-V, 2.5-V, 3.3-V,or 5-V VREF2
- 1.8-V VREF1 and 2.5-V, 3.3-V, or 5-VVREF2
- 2.5-V VREF1 and 3.3-V or 5-VVREF2
- 3.3-V VREF1 and 5-V VREF2
- Provides Bidirectional Voltage Translation with no Direction Pin
- Low 3.5-Ω ON-state ResistanceBetween Input and Output Ports Provides Less SignalDistortion
- Open-drain I2C I/O ports (SCL1, SDA1, SCL2, andSDA2)
- 5-V Tolerant I2C I/O Ports to Support Mixed-mode SignalOperation
- High-impedance SCL1, SDA1, SCL2, and SDA2 pins for EN = Low
- Lockup-free Operation for Isolation when EN=Low
- Flow-through Pinout for Ease of Printed-circuit-board Trace Routing
- Latch-up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
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