Data sheet acquired from Harris Semiconductor.
DescriptionCD4504BMG4 hex voltage level-shifter consists of six circuits which shift input signals from the VCC logic levelto the VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCCHIGH logic state. When the SELECT input is a LOW logic state, each circuit translates signals from one CMOS level to another.
The CD4504BMG4 types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Feature
- Independence of power-supply sequence considerations - VCC can exceed VDD; input signals can exceed both VCC and VDD
- Up and down level-shifting capability
- Shiftable input threshold for either CMOS or TTL compatibility
- Standardized symmetrical output characteristics
- 100% tested for quiescent current @ 20 V
- Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- 5V, 10 V, and 15 V parametric ratings
- Meets all requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of ’B’ SeriesCMOS Devices"
Data sheet acquired from Harris Semiconductor.
DescriptionCD4504B hex voltage level-shifter consists of six circuits which shift input signals from the VCC logic levelto the VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCCHIGH logic state. When the SELECT input is a LOW logic state, each circuit translates signals from one CMOS level to another.
The CD4504B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
