Feature
• High Speed: tPD = 4.5 ns (Typ) at VCC = 3.3 V
• Low Power Dissipation: ICC = 4 μA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• Chip Complexity: FETs = 100; Equivalent Gates = 25
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
• Pb−Free Packages are Available*
